During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.
One type of tests typically performed on integrated circuits such as memory devices are tests of the timing margins of the integrated circuits. For example, one memory device timing parameter that is normally tested is the skew of a data strobe signals DQS with respect to last read data signal DQ to become valid, which is abbreviated as tDQSQ. Another memory device timing parameter that is normally tested is the DQ-DQS hold time, abbreviated as tQH, which is the skew of the DQS signal with respect to the first DQ signal to become invalid. In synchronous memory devices, read data signals DQ are output from the memory devices in synchronism with a data strobe signal DQS. With reference to FIG. 1, the data strobe signal DQS transitions active at time t0, and the read data signals DQ then become valid. The maximum time needed for the last of the read data signals DQ to become valid after the transition of DQS at t0, i.e., tDQSQ, is normally specified for a memory device. The timing parameter tDQSQ thus represents the maximum acceptable skew between the last of the read data signals DQ that becomes valid and the data strobe signal DQS. Similarly, the minimum time that the earliest of the read data signals DQ becomes invalid after the transition of DQS at t0, i.e., tQH, is also normally specified for a memory device.
The time between tDQSQ and tQH is the data valid period. The length of the data valid period may be excessively reduced by any increase in the DQS-DQ skew beyond the specified maximum tDQSQ or any decrease of the DQ-DQS hold time from the specified tQH. As the length of the data hold period gets smaller, it becomes more difficult for the memory device to position transitions of the DQS signal at the start of the data valid period. It is therefore important to determine the data set-up and data hold times of a memory device being tested to ensure that a sufficient data valid period can be achieved.
The above-described testing environment works well in many applications to test the timing parameters of integrated circuits such as memory devices. However, the testing environment is not without its limitations and disadvantages. For example, it is very difficult to test various timing characteristics of the integrated circuits, particularly at the high operating speeds for which such integrated circuits are designed. This difficulty in testing timing characteristics results primarily from the propagation delays in the cable coupling the tester to the test head. The cables that are typically used in such testing environments are often fairly long, thus making the delays of signals coupled to and from the integrated circuits correspondingly long and often difficult to predict.
Another problem with the above-described testing environment is that it may not accurately simulate the conditions in which the integrated circuits will actually be used. In particular, the integrated circuits, and particularly the timing parameters of integrated circuits, are not generally tested during use in an actual operating environment and after a substantial period has lapsed. Therefore, even if the timing parameters of the integrated circuit were within specification when the integrated circuit was shipped from a fabrication facility, there can be no assurance that the timing parameters are within a specified range during use, particularly after a substantial period of time. Also, it is difficult to measure a skew between two output ports as opposed to measuring a skew between an input port and an output port.
There is therefore a need for a testing system and method that can be easily fabricated in an integrated circuit to allow the timing parameters of an integrated circuit to be accurately tested during actual use of the integrated circuit.